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1. general description the 74lvc8t245; 74lvch8t245 are 8-bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. they feature two data input-output ports (pins an and bn), a directi on control input (dir), an output enable input (oe ) and dual supply pins (v cc(a) and v cc(b) ). both v cc(a) and v cc(b) can be supplied at any voltage between 1.2 v and 5.5 v making the device suitable for translating between any of the low voltage nodes (1.2 v, 1.5 v, 1.8 v, 2.5 v, 3.3 v and 5.0 v). pins an, oe and dir are referenced to v cc(a) and pins bn are referenced to v cc(b) . a high on dir allows transmission from an to bn and a low on di r allows transmission from bn to an. the output enable input (oe ) can be used to disable the outputs so the buses are effectively isolated. the devices are fully specified for part ial power-down app lications using i off . the i off circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. in suspend mode when either v cc(a) or v cc(b) are at gnd level, both a port and b port ar e in the high-impedance off-state. active bus hold circuitry in the 74lvch8t245 holds unused or floating data inputs at a valid logic level. 2. features and benefits ? wide supply voltage range: ? v cc(a) : 1.2 v to 5.5 v ? v cc(b) : 1.2 v to 5.5 v ? high noise immunity ? complies with jedec standards: ? jesd8-7 (1.2 v to 1.95 v) ? jesd8-5 (1.8 v to 2.7 v) ? jesd8c (2.7 v to 3.6 v) ? jesd36 (4.5 v to 5.5 v) ? esd protection: ? hbm jesd22-a114f class 3a exceeds 4000 v ? mm jesd22-a115-b exceeds 200 v ? cdm jesd22-c101e exceeds 1000 v ? maximum data rates: ? 420 mbps (3.3 v to 5.0 v translation) ? 210 mbps (translate to 3.3 v)) ? 140 mbps (translate to 2.5 v) ? 75 mbps (translate to 1.8 v) 74lvc8t245; 74lvch8t245 8-bit dual supply translat ing transceiver; 3-state rev. 3 ? 12 december 2011 product data sheet
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 2 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state ? 60 mbps (translate to 1.5 v) ? suspend mode ? latch-up performance exceeds 100 ma per jesd 78b class ii ? ? 24 ma output drive (v cc =3.0v) ? inputs accept voltages up to 5.5 v ? low power consumption: 30 ? a maximum i cc ? i off circuitry provides partial power-down mode operation ? multiple package options ? specified from ? 40 ? cto+85 ? c and ? 40 ? cto+125 ? c 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74lvc8t245pw ? 40 ? c to +125 ? c tssop24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 74LVCH8T245PW 74lvc8t245bq ? 40 ? c to +125 ? c dhvqfn24 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 ? 5.5 ? 0.85 mm sot815-1 74lvch8t245bq fig 1. logic symbol 001aai472 oe dir v cc(a) v cc(b) 22 2 3 a1 a2 a3 a4 a5 a6 a7 a8 b1 b2 b3 b4 b5 b6 b7 b8 4567891 0 21 20 19 18 17 16 15 14
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 3 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state 5. pinning information 5.1 pinning fig 2. logic diagram (one channel) 001aai473 to other seven channels dir a1 v cc(a) v cc(b) oe b1 (1) this is not a supply pin, the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad however if it is soldered the solder land should remain floating or be connected to gnd. fig 3. pin configuration sot355-1 (tssop24) fi g 4. pin configuration sot815-1 (dhvqfn24) 74lvc8t245 74lvch8t245 v cc(a) v cc(b) dir v cc(b) a1 oe a2 b1 a3 b2 a4 b3 a5 b4 a6 b5 a7 b6 a8 b7 gnd b8 gnd gnd 001aak436 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 001aak437 74lvc8t245 74lvch8t245 transparent top view b8 a8 gnd b7 a7 b6 a6 b5 a5 b4 a4 b3 a3 b2 a2 b1 a1 oe dir v cc(b) gnd gnd v cc(a) v cc(b) 11 14 10 15 9 16 8 17 7 18 6 19 5 20 4 21 3 22 2 23 12 13 1 24 terminal 1 index area gnd (1)
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 4 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state 5.2 pin description [1] all gnd pins must be connected to ground (0 v). 6. functional description [1] h = high voltage level; l = low voltage level; x = don?t care; z = high-impedance off-state. [2] the an inputs/outputs, dir and oe input circuit is referenced to v cc(a) ; the bn inputs/outputs circuit is referenced to v cc(b) . [3] if at least one of v cc(a) or v cc(b) is at gnd level, the device goes into suspend mode. 7. limiting values table 2. pin description symbol pin description v cc(a) 1 supply voltage a (an inputs/outputs, oe and dir inputs are referenced to v cc(a) ) dir 2 direction control a1 to a8 3, 4, 5, 6, 7, 8, 9, 10 data input or output gnd [1] 11 ground (0 v) gnd [1] 12 ground (0 v) gnd [1] 13 ground (0 v) b1 to b8 21, 20, 19, 18, 17, 16, 15, 14 data input or output oe 22 output enable input (active low) v cc(b) 23 supply voltage b (bn inputs/outputs are referenced to v cc(b) ) v cc(b) 24 supply voltage b (bn inputs/outputs are referenced to v cc(b) ) table 3. function table [1] supply voltage input input/output [3] v cc(a) , v cc(b) oe [2] dir [2] an [2] bn [2] 1.2 v to 5.5 v l l an = bn input 1.2 v to 5.5 v l h input bn = an 1.2 v to 5.5 v h x z z gnd [3] xxzz table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc(a) supply voltage a ? 0.5 +6.5 v v cc(b) supply voltage b ? 0.5 +6.5 v i ik input clamping current v i <0v ? 50 - ma v i input voltage [1] ? 0.5 +6.5 v i ok output clamping current v o <0v ? 50 - ma v o output voltage active mode [1] [2] [3] ? 0.5 v cco +0.5 v suspend or 3-state mode [1] ? 0.5 +6.5 v i o output current v o =0vtov cco [2] - ? 50 ma i cc supply current i cc(a) or i cc(b) ; per v cc pin - 100 ma
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 5 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state [1] the minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are obs erved. [2] v cco is the supply voltage associated with the output port. [3] v cco + 0.5 v should not exceed 6.5 v. [4] for tssop24 package: p tot derates linearly at 5.5 mw/k above 60 ? c. for dhvqfn24 package: p tot derates linearly at 4.5 mw/k above 60 ? c. 8. recommended operating conditions [1] v cco is the supply voltage associated with the output port. [2] v cci is the supply voltage associated with the input port. 9. static characteristics i gnd ground current per gnd pin ? 100 - ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = ? 40 ? c to +125 ?c [4] -5 0 0m w table 4. limiting values ?continued in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit table 5. recommended operating conditions symbol parameter conditions min max unit v cc(a) supply voltage a 1.2 5.5 v v cc(b) supply voltage b 1.2 5.5 v v i input voltage 0 5.5 v v o output voltage active mode [1] 0v cco v suspend or 3-state mode 0 5.5 v t amb ambient temperature ? 40 +125 ?c ? t/ ? v input transition rise and fall rate v cci = 1.2 v [2] - 20 ns/v v cci = 1.4 v to 1.95 v - 20 ns/v v cci = 2.3 v to 2.7 v - 20 ns/v v cci = 3 v to 3.6 v - 10 ns/v v cci = 4.5 v to 5.5 v - 5 ns/v table 6. typical static characteristics at t amb = 25 ?c at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit v oh high-level output voltage v i = v ih or v il [1] i o = ? 3 ma; v cco = 1.2 v - 1.09 - v v ol low-level output voltage v i = v ih or v il i o = 3 ma; v cco =1.2v [1] -0.07-v i i input leakage current dir, oe input; v i = 0 v to 5.5 v; v cci = 1.2 v to 5.5 v [2] -- ? 1 ? a i bhl bus hold low current a or b port; v i =0.42v;v cci =1.2v [2] -19- ? a i bhh bus hold high current a or b port; v i =0.78v;v cci =1.2v [2] - ? 19 - ? a
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 6 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state [1] v cco is the supply voltage associated with the output port. [2] v cci is the supply voltage associated with the data input port. [3] to guarantee the node switches, an external driver must source/sink at least i bhlo / i bhho when the input is in the range v il to v ih . i bhlo bus hold low overdrive current a or b port; v cci = 1.2 v [2] [3] -19- ? a i bhho bus hold high overdrive current a or b port; v cci = 1.2 v [2] [3] - ? 19 - ? a i oz off-state output current a or b port; v o =0 vor v cco ; v cco = 1.2 v to 5.5 v [1] -- ? 1 ? a suspend mode a port; v o =0vorv cco ; v cc(a) = 5.5 v; v cc(b) =0v [1] -- ? 1 ? a suspend mode b port; v o =0vorv cco ; v cc(a) =0 v; v cc(b) =5.5v [1] -- ? 1 ? a i off power-off leakage current a port; v i or v o = 0 v to 5.5 v; v cc(a) =0v;v cc(b) = 1.2 v to 5.5 v -- ? 1 ? a b port; v i or v o = 0 v to 5.5 v; v cc(b) =0v;v cc(a) = 1.2 v to 5.5 v -- ? 1 ? a c i input capacitance dir, oe input; v i = 0 v or 3.3 v; v cc(a) =3.3v - 3 - pf c i/o input/output capacitance a and b port; v o =3.3vor0v; v cc(a) =v cc(b) =3.3v -6.5-pf table 6. typical static characteristics at t amb = 25 ?c ?continued at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit table 7. static characteristics at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min max min max v ih high-level input voltage data input [1] v cci = 1.2 v 0.8v cci -0.8v cci -v v cci = 1.4 v to 1.95 v 0.65v cci -0.65v cci -v v cci = 2.3 v to 2.7 v 1.7 - 1.7 - v v cci = 3.0 v to 3.6 v 2.0 - 2.0 - v v cci = 4.5 v to 5.5 v 0.7v cci -0.7v cci -v dir, oe input v cci = 1.2 v 0.8v cc(a) -0.8v cc(a) -v v cci = 1.4 v to 1.95 v 0.65v cc(a) -0.65v cc(a) -v v cci = 2.3 v to 2.7 v 1.7 - 1.7 - v v cci = 3.0 v to 3.6 v 2.0 - 2.0 - v v cci = 4.5 v to 5.5 v 0.7v cc(a) -0.7v cc(a) -v
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 7 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state v il low-level input voltage data input [1] v cci = 1.2 v - 0.2v cci -0.2v cci v v cci = 1.4 v to 1.95 v - 0.35v cci -0.35v cci v v cci = 2.3 v to 2.7 v - 0.7 - 0.7 v v cci = 3.0 v to 3.6 v - 0.8 - 0.8 v v cci = 4.5 v to 5.5 v - 0.3v cci -0.3v cci v dir, oe input v cci = 1.2 v - 0.2v cc(a) -0.2v cc(a) v v cci = 1.4 v to 1.95 v - 0.35v cc(a) - 0.35v cc(a) v v cci = 2.3 v to 2.7 v - 0.7 - 0.7 v v cci = 3.0 v to 3.6 v - 0.8 - 0.8 v v cci = 4.5 v to 5.5 v - 0.3v cc(a) -0.3v cc(a) v v oh high-level output voltage v i = v ih i o = ? 100 ? a; v cco = 1.2 v to 4.5 v [2] v cco ? 0.1 - v cco ? 0.1 - v i o = ? 6ma; v cco = 1.4 v 1.0 - 1.0 - v i o = ? 8ma; v cco = 1.65 v 1.2 - 1.2 - v i o = ? 12 ma; v cco = 2.3 v 1.9 - 1.9 - v i o = ? 24 ma; v cco = 3.0 v 2.4 - 2.4 - v i o = ? 32 ma; v cco = 4.5 v 3.8 - 3.8 - v v ol low-level output voltage v i = v il [2] i o = 100 ? a; v cco = 1.2 v to 4.5 v - 0.1 - 0.1 v i o = 6 ma; v cco = 1.4 v - 0.3 - 0.3 v i o = 8 ma; v cco = 1.65 v - 0.45 - 0.45 v i o = 12 ma; v cco = 2.3 v - 0.3 - 0.3 v i o = 24 ma; v cco = 3.0 v - 0.55 - 0.55 v i o = 32 ma; v cco = 4.5 v - 0.55 - 0.55 v i i input leakage current dir, oe input; v i = 0 v to 5.5 v; v cci = 1.2 v to 5.5 v - ? 2- ? 10 ? a i bhl bus hold low current a or b port [1] v i = 0.49 v; v cci =1.4v 15 - 10 - ? a v i = 0.58 v; v cci =1.65v 25 - 20 - ? a v i = 0.70 v; v cci =2.3v 45 - 45 - ? a v i = 0.80 v; v cci =3.0v 100 - 80 - ? a v i = 1.35 v; v cci =4.5v 100 - 100 - ? a table 7. static characteristics ?continued at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min max min max
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 8 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state i bhh bus hold high current a or b port [1] v i = 0.91 v; v cci =1.4v ? 15 - ? 10 - ? a v i = 1.07 v; v cci =1.65v ? 25 - ? 20 - ? a v i = 1.70 v; v cci =2.3v ? 45 - ? 45 - ? a v i = 2.00 v; v cci =3.0v ? 100 - ? 80 - ? a v i = 3.15 v; v cci =4.5v ? 100 - ? 100 - ? a i bhlo bus hold low overdrive current a or b port [1] [3] v cci = 1.6 v 125 - 125 - ? a v cci = 1.95 v 200 - 200 - ? a v cci = 2.7 v 300 - 300 - ? a v cci = 3.6 v 500 - 500 - ? a v cci = 5.5 v 900 - 900 - ? a i bhho bus hold high overdrive current a or b port [1] [3] v cci = 1.6 v ? 125 - ? 125 - ? a v cci = 1.95 v ? 200 - ? 200 - ? a v cci = 2.7 v ? 300 - ? 300 - ? a v cci = 3.6 v ? 500 - ? 500 - ? a v cci = 5.5 v ? 900 - ? 900 - ? a i oz off-state output current a or b port; v o =0vorv cco ; v cco = 1.2 v to 5.5 v [2] - ? 2- ? 10 ? a suspend mode a port; v o =0vorv cco ; v cc(a) = 5.5 v; v cc(b) =0v [2] - ? 2- ? 10 ? a suspend mode b port; v o =0vorv cco ; v cc(a) =0 v; v cc(b) =5.5v [2] - ? 2- ? 10 ? a i off power-off leakage current a port; v i or v o =0vto5.5v; v cc(a) =0v; v cc(b) = 1.2 v to 5.5 v - ? 2- ? 10 ? a b port; v i or v o =0vto5.5v; v cc(b) =0v; v cc(a) = 1.2 v to 5.5 v - ? 2- ? 10 ? a table 7. static characteristics ?continued at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min max min max
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 9 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state [1] v cci is the supply voltage associated with the data input port. [2] v cco is the supply voltage associated with the output port. [3] to guarantee the node switches, an external driver must source/sink at least i bhlo / i bhho when the input is in the range v il to v ih . [4] for non bus hold parts only (74lvc8t245). i cc supply current a port; v i = 0 v or v cci ; i o = 0 a [1] v cc(a) , v cc(b) = 1.2 v to 5.5 v - 15 - 20 ? a v cc(a) = 5.5 v; v cc(b) = 0 v - 15 - 20 ? a v cc(a) = 0 v; v cc(b) = 5.5 v ? 2- ? 4- ? a b port; v i = 0 v or v cci ; i o = 0 a v cc(a) , v cc(b) = 1.2 v to 5.5 v - 15 - 20 ? a v cc(b) = 0 v; v cc(a) = 5.5 v ? 2- ? 4- ? a v cc(b) = 5.5 v; v cc(a) = 0 v - 15 - 20 ? a a plus b port (i cc(a) + i cc(b) ); i o =0a; v i =0 vor v cci v cc(a) , v cc(b) = 1.2 v to 5.5 v - 25 - 30 ? a ? i cc additional supply current per input; v cc(a) ,v cc(b) = 3.0 v to 5.5 v dir and oe input; dir or oe input at v cc(a) ? 0.6 v; aportatv cc(a) or gnd; b port = open -50-75 ? a a port; a port at v cc(a) ? 0.6 v; dir at v cc(a) ; b port = open [4] -50-75 ? a b port; b port at v cc(b) ? 0.6 v; dir at gnd; a port = open [4] -50-75 ? a table 7. static characteristics ?continued at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min max min max
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 10 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state 10. dynamic characteristics [1] t pd is the same as t plh and t phl ; t dis is the same as t plz and t phz ; t en is the same as t pzl and t pzh . [1] t pd is the same as t plh and t phl ; t dis is the same as t plz and t phz ; t en is the same as t pzl and t pzh . [1] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? (c l ? v cc 2 ? f o ) = sum of the outputs. [2] f i = 10 mhz; v i =gndtov cc ; t r = t f = 1 ns; c l = 0 pf; r l = ? ? . table 8. typical dynamic characteristics at v cc(a) = 1.2 v and t amb = 25 ?c [1] voltages are referenced to gnd (ground = 0 v); for test circuit see figure 7 ; for waveforms see figure 5 and figure 6 . symbol parameter conditions v cc(b) unit 1.2 v 1.5 v 1.8 v 2.5 v 3.3 v 5.0 v t pd propagation delay an to bn 11.0 8.5 7.4 6.2 5.7 5.4 ns bn to an 11.0 10.0 9.5 9.1 8.9 8.9 ns t dis disable time oe to an 9.5 9.5 9.5 9.5 9.5 9.5 ns oe to bn 10.2 8.2 7.8 6.7 7.3 6.4 ns t en enable time oe to an 13.5 13.5 13.5 13.5 13.5 13.5 ns oe to bn 13.6 10.3 8.9 7.5 7.1 7.0 ns table 9. typical dynamic characteristics at v cc(b) = 1.2 v and t amb = 25 ?c [1] voltages are referenced to gnd (ground = 0 v); for test circuit see figure 7 ; for waveforms see figure 5 and figure 6 . symbol parameter conditions v cc(a) unit 1.2 v 1.5 v 1.8 v 2.5 v 3.3 v 5.0 v t pd propagation delay an to bn 11.0 10.0 9.5 9.1 8.9 8.8 ns bn to an 11.0 8.5 7.3 6.2 5.7 5.4 ns t dis disable time oe to an 9.5 6.8 5.4 3.8 4.1 3.1 ns oe to bn 10.2 9.1 8.6 8.1 7.8 7.8 ns t en enable time oe to an 13.5 9.0 6.9 4.8 3.8 3.2 ns oe to bn 13.6 12.5 12.0 11.5 11.4 11.4 ns table 10. typical power dissipation capacitance at v cc(a) = v cc(b) and t amb = 25 ?c [1] [2] voltages are referenced to gnd (ground = 0 v). symbol parameter conditions v cc(a) and v cc(b) unit 1.8 v 2.5 v 3.3 v 5.0 v c pd power dissipation capacitance a port: (direction a to b); b port: (direction b to a) 1112pf a port: (direction b to a); b port: (direction a to b) 13 13 13 13 pf
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 11 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state [1] t pd is the same as t plh and t phl ; t dis is the same as t plz and t phz ; t en is the same as t pzl and t pzh . table 11. dynamic characteristics for temperature range ? 40 ? c to +85 ?c [1] voltages are referenced to gnd (ground = 0 v); for test circuit see figure 7 ; for wave forms see figure 5 and figure 6 . symbol parameter conditions v cc(b) unit 1.5 v ? 0.1 v 1.8 v ? 0.15 v 2.5 v ? 0.2 v 3.3 v ? 0.3 v 5.0 v ? 0.5 v min max min max min max min max min max v cc(a) = 1.5 v ? 0.1 v t pd propagation delay an to bn 1.7 27 1.7 23 1.3 18 1.0 15 0.8 13 ns bn to an 0.9 27 0.9 25 0.8 23 0.7 23 0.7 22 ns t dis disable time oe to an 1.5 30 1.5 30 1.5 30 1.5 30 1.4 30 ns oe to bn 2.4 34 2.4 33 1.9 15 1.7 14 1.3 12 ns t en enable time oe to an 0.4 34 0.4 34 0.4 34 0.4 34 0.4 34 ns oe to bn 1.8 36 1.8 34 1.5 18 1.2 15 0.9 13 ns v cc(a) = 1.8 v ? 0.15 v t pd propagation delay an to bn 1.7 25 1.7 21.9 1.3 9.2 1.0 7.4 0.8 7.1 ns bn to an 0.9 23 0.9 23.8 0.8 23.6 0.7 23.4 0.7 23.4 ns t dis disable time oe to an 1.5 30 1.5 29.6 1.5 29.4 1.5 29.3 1.4 29.2 ns oe to bn 2.4 33 2.4 32.2 1.9 13.1 1.7 12.0 1.3 10.3 ns t en enable time oe to an 0.4 24 0.4 24.0 0.4 23.8 0.4 23.7 0.4 23.7 ns oe to bn 1.8 34 1.8 32.0 1.5 16.0 1.2 12.6 0.9 10.8 ns v cc(a) = 2.5 v ? 0.2 v t pd propagation delay an to bn 1.5 23 1.5 21.4 1.2 9.0 0.8 6.2 0.6 4.8 ns bn to an 1.2 18 1.2 9.3 1.0 9.1 1.0 8.9 0.9 8.8 ns t dis disable time oe to an 1.4 9.0 1.4 9.0 1.4 9.0 1.4 9.0 1.4 9.0 ns oe to bn 2.3 31 2.3 29.6 1.8 11.0 1.7 9.3 0.9 6.9 ns t en enable time oe to an 1.0 10.9 1.0 10.9 1.0 10.9 1.0 10.9 1.0 10.9 ns oe to bn 1.7 32 1.7 28.2 1.5 12.9 1.2 9.4 1.0 6.9 ns v cc(a) = 3.3 v ? 0.3 v t pd propagation delay an to bn 1.5 23 1.5 21.2 1.1 8.8 0.8 6.3 0.5 4.4 ns bn to an 0.8 15 0.8 7.2 0.8 6.2 0.7 6.1 0.6 6.0 ns t dis disable time oe to an 1.6 8.2 1.6 8.2 1.6 8.2 1.6 8.2 1.6 8.2 ns oe to bn 2.1 30 2.1 29.0 1.7 10.3 1.5 8.6 0.8 6.3 ns t en enable time oe to an 0.8 8.1 0.8 8.1 0.8 8.1 0.8 8.1 0.8 8.1 ns oe to bn 1.8 31 1.8 27.7 1.4 12.4 1.1 8.5 0.9 6.4 ns v cc(a) = 5.0 v ? 0.5 v t pd propagation delay an to bn 1.5 22 1.5 21.4 1.0 8.8 0.7 6.0 0.4 4.2 ns bn to an 0.7 13 0.7 7.0 0.4 4.8 0.3 4.5 0.3 4.3 ns t dis disable time oe to an 0.3 5.4 0.3 5.4 0.3 5.4 0.3 5.4 0.3 5.4 ns oe to bn 2.0 30 2.0 28.7 1.6 9.7 1.4 8.0 0.7 5.7 ns t en enable time oe to an 0.7 6.4 0.7 6.4 0.7 6.4 0.7 6.4 0.7 6.4 ns oe to bn 1.5 31 1.5 27.6 1.3 11.4 1.0 8.1 0.9 6.0 ns
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 12 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state [1] t pd is the same as t plh and t phl ; t dis is the same as t plz and t phz ; t en is the same as t pzl and t pzh . table 12. dynamic characteristics for temperature range ? 40 ? c to +125 ?c [1] voltages are referenced to gnd (ground = 0 v); for test circuit see figure 7 ; for wave forms see figure 5 and figure 6 . symbol parameter conditions v cc(b) unit 1.5 v ? 0.1 v 1.8 v ? 0.15 v 2.5 v ? 0.2 v 3.3 v ? 0.3 v 5.0 v ? 0.5 v min max min max min max min max min max v cc(a) = 1.5 v ? 0.1 v t pd propagation delay an to bn 1.7 32 1.7 27 1.3 21 1.0 18 0.8 16 ns bn to an 0.9 32 0.9 30 0.8 28 0.7 28 0.7 26 ns t dis disable time oe to an 1.5 34 1.5 34 1.5 34 1.5 34 1.4 34 ns oe to bn 2.4 41 2.4 40 1.9 18 1.7 17 1.3 15 ns t en enable time oe to an 0.4 40 0.4 40 0.4 40 0.4 40 0.4 40 ns oe to bn 1.8 43 1.8 41 1.5 22 1.2 18 0.9 16 ns v cc(a) = 1.8 v ? 0.15 v t pd propagation delay an to bn 1.7 30 1.7 25.9 1.3 13.2 1.0 11.4 0.8 11.1 ns bn to an 0.9 27 0.9 28.8 0.8 27.6 0.7 27.4 0.7 27.4 ns t dis disable time oe to an 1.5 34 1.5 33.6 1.5 33.4 1.5 33.3 1.4 33.2 ns oe to bn 2.4 40 2.4 36.2 1.9 17.1 1.7 16.0 1.3 14.3 ns t en enable time oe to an 0.4 28 0.4 28 0.4 27.8 0.4 27.7 0.4 27.7 ns oe to bn 1.8 41 1.8 40 1.5 20 1.2 16.6 0.9 14.8 ns v cc(a) = 2.5 v ? 0.2 v t pd propagation delay an to bn 1.5 28 1.5 25.4 1.2 13 0.8 10.2 0.6 8.8 ns bn to an 1.2 23 1.2 13.3 1.0 13.1 1.0 12.9 0.9 12.8 ns t dis disable time oe to an 1.4 13 1.4 13 1.4 13 1.4 13 1.4 13 ns oe to bn 2.3 37 2.3 33.6 1.8 15 1.7 14.3 0.9 10.9 ns t en enable time oe to an 1.0 17.2 1.0 17.2 1.0 17.3 1.0 17.2 1.0 17.3 ns oe to bn 1.7 38 1.7 32.2 1.5 18.1 1.2 14.1 1.0 11.2 ns v cc(a) = 3.3 v ? 0.3 v t pd propagation delay an to bn 1.5 28 1.5 25.2 1.1 12.8 0.8 10.3 0.5 10.4 ns bn to an 0.8 18 0.8 11.2 0.8 10.2 0.7 10.1 0.6 10 ns t dis disable time oe to an 1.6 12.2 1.6 12.2 1.6 12.2 1.6 12.2 1.6 12.2 ns oe to bn 2.1 36 2.1 33 1.7 14.3 1.5 12.6 0.8 10.3 ns t en enable time oe to an 0.8 14.1 0.8 14.1 0.8 13.6 0.8 13.2 0.8 13.6 ns oe to bn 1.8 37 1.8 31.7 1.4 18.4 1.1 12.9 0.9 10.9 ns v cc(a) = 5.0 v ? 0.5 v t pd propagation delay an to bn 1.5 26 1.5 25.4 1.0 12.8 0.7 10 0.4 8.2 ns bn to an 0.7 16 0.7 11 0.4 8.8 0.3 8.5 0.3 8.3 ns t dis disable time oe to an 0.3 9.4 0.3 9.4 0.3 9.4 0.3 9.4 0.3 9.4 ns oe to bn 2.0 36 2.0 32.7 1.6 13.7 1.4 12 0.7 9.7 ns t en enable time oe to an 0.7 10.9 0.7 10.9 0.7 10.9 0.7 10.9 0.7 10.9 ns oe to bn 1.5 37 1.5 31.6 1.3 18.4 1.0 13.7 0.9 10.7 ns
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 13 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state 11. waveforms [1] v cci is the supply voltage associated with the data input port. [2] v cco is the supply voltage associated with the output port. measurement points are given in table 13 . v ol and v oh are typical output voltage levels that occur with the output load. fig 5. the data input (an, bn) to outp ut (bn, an) propagation delay times 001aai475 v m v m v i an, bn input gnd v oh bn, an output v ol t phl t plh measurement points are given in table 13 . v ol and v oh are typical output voltage levels that occur with the output load. fig 6. enable and disable times 001aai474 t plz t phz outputs disabled outputs enabled v y v x outputs enabled output low-to-off off-to-low output high-to-off off-to-high oe input v ol v oh v cco v i v m gnd gnd t pzl t pzh v m v m table 13. measurement points supply voltage input [1] output [2] v cc(a) , v cc(b) v m v m v x v y 1.2 v to 1.6 v 0.5v cci 0.5v cco v ol +0.1v v oh ? 0.1 v 1.65 v to 2.7 v 0.5v cci 0.5v cco v ol +0.15v v oh ? 0.15 v 3.0 v to 5.5 v 0.5v cci 0.5v cco v ol +0.3v v oh ? 0.3 v
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 14 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state [1] v cci is the supply voltage associated with the data input port. [2] dv/dt ? 1.0 v/ns. [3] v cco is the supply voltage associated with the output port. test data is given in table 14 . r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance. v ext = external voltage for measuring switching times. fig 7. load circuitry for switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aae331 v ext v cc v i v o dut c l r t r l r l g table 14. test data supply voltage input load v ext v cc(a) , v cc(b) v i [1] ? t/ ? v [2] c l r l t plh , t phl t pzh , t phz t pzl , t plz [3] 1.2 v to 5.5 v v cci ? 1.0ns/v 15pf 2k ? open gnd 2v cco
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 15 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state 12. typical propagation delay characteristics a. high to low propagation delay (a to b) b. low to high propagation delay (a to b) c. high to low propagation delay (b to a) d. low to high propagation delay (b to a) (1) v cc(b) = 1.2 v. (2) v cc(b) = 1.5 v. (3) v cc(b) = 1.8 v. (4) v cc(b) = 2.5 v. (5) v cc(b) = 3.3 v. (6) v cc(b) = 5.0 v. fig 8. typical propagation delay versus load capacitance; t amb = 25 ?c; v cc(a) =1.2v c l (pf) 35 25 530 20 10 015 001aal268 6 2 10 14 4 8 12 t phl (ns) 0 (3) (4) (5) (6) (1) (2) c l (pf) 35 25 530 20 10 015 001aal269 6 2 10 14 4 8 12 t plh (ns) 0 (4) (5) (6) (1) (3) (2) c l (pf) 35 25 530 20 10 015 001aal270 6 2 10 14 4 8 12 t phl (ns) 0 (1) (2) (3) (4) (5) (6) c l (pf) 35 25 530 20 10 015 001aal271 6 2 10 14 4 8 12 t plh (ns) 0 (1) (2) (3) (4) (5) (6)
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 16 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state a. high to low propagation delay (a to b) b. low to high propagation delay (a to b) c. high to low propagation delay (b to a) d. low to high propagation delay (b to a) (1) v cc(b) = 1.2 v. (2) v cc(b) = 1.5 v. (3) v cc(b) = 1.8 v. (4) v cc(b) = 2.5 v. (5) v cc(b) = 3.3 v. (6) v cc(b) = 5.0 v. fig 9. typical propagation delay versus load capacitance; t amb = 25 ?c; v cc(a) =1.5v c l (pf) 35 25 530 20 10 015 001aal272 6 2 10 14 4 8 12 t phl (ns) 0 (3) (4) (5) (6) (1) (2) c l (pf) 35 25 530 20 10 015 001aal273 6 2 10 14 4 8 12 t plh (ns) 0 (3) (4) (5) (6) (1) (2) c l (pf) 35 25 530 20 10 015 001aal274 6 2 10 14 4 8 12 t phl (ns) 0 (1) (2) (3) (4) (5) (6) c l (pf) 35 25 530 20 10 015 001aal275 6 2 10 14 4 8 12 t plh (ns) 0 (1) (2) (3) (4) (5) (6)
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 17 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state a. high to low propagation delay (a to b) b. low to high propagation delay (a to b) c. high to low propagation delay (b to a) d. low to high propagation delay (b to a) (1) v cc(b) = 1.2 v. (2) v cc(b) = 1.5 v. (3) v cc(b) = 1.8 v. (4) v cc(b) = 2.5 v. (5) v cc(b) = 3.3 v. (6) v cc(b) = 5.0 v. fig 10. typical propagation delay versus load capacitance; t amb = 25 ?c; v cc(a) =1.8v c l (pf) 35 25 530 20 10 015 001aal276 6 2 10 14 4 8 12 t phl (ns) 0 (4) (5) (6) (1) (2) (3) c l (pf) 35 25 530 20 10 015 001aal277 6 2 10 14 4 8 12 t plh (ns) 0 (4) (5) (6) (1) (2) (3) c l (pf) 35 25 530 20 10 015 001aal278 6 2 10 14 4 8 12 t phl (ns) 0 (1) (2) (3) (4) (5) (6) c l (pf) 35 25 530 20 10 015 001aal279 6 2 10 14 4 8 12 t plh (ns) 0 (1) (2) (3) (4) (5) (6)
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 18 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state a. high to low propagation delay (a to b) b. low to high propagation delay (a to b) c. high to low propagation delay (b to a) d. low to high propagation delay (b to a) (1) v cc(b) = 1.2 v. (2) v cc(b) = 1.5 v. (3) v cc(b) = 1.8 v. (4) v cc(b) = 2.5 v. (5) v cc(b) = 3.3 v. (6) v cc(b) = 5.0 v. fig 11. typical propagation delay versus load capacitance; t amb = 25 ?c; v cc(a) =2.5v c l (pf) 35 25 530 20 10 015 001aal280 6 2 10 14 4 8 12 t phl (ns) 0 (4) (5) (6) (1) (3) (2) c l (pf) 35 25 530 20 10 015 001aal281 6 2 10 14 4 8 12 t plh (ns) 0 (4) (5) (6) (1) (3) (2) c l (pf) 35 25 530 20 10 015 001aal282 6 2 10 14 4 8 12 t phl (ns) 0 (1) (2) (3) (4) (5) (6) c l (pf) 35 25 530 20 10 015 001aal283 6 2 10 14 4 8 12 t plh (ns) 0 (1) (2) (3) (4) (5) (6)
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 19 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state a. high to low propagation delay (a to b) b. low to high propagation delay (a to b) c. high to low propagation delay (b to a) d. low to high propagation delay (b to a) (1) v cc(b) = 1.2 v. (2) v cc(b) = 1.5 v. (3) v cc(b) = 1.8 v. (4) v cc(b) = 2.5 v. (5) v cc(b) = 3.3 v. (6) v cc(b) = 5.0 v. fig 12. typical propagation delay versus load capacitance; t amb = 25 ?c; v cc(a) =3.3v c l (pf) 35 25 530 20 10 015 001aal284 6 2 10 14 4 8 12 t phl (ns) 0 (4) (5) (6) (1) (2) (3) c l (pf) 35 25 530 20 10 015 001aal285 6 2 10 14 4 8 12 t plh (ns) 0 (4) (5) (6) (1) (2) (3) c l (pf) 35 25 530 20 10 015 001aal286 6 2 10 14 4 8 12 t phl (ns) 0 (1) (2) (3) (4) (5) (6) c l (pf) 35 25 530 20 10 015 001aal287 6 2 10 14 4 8 12 t plh (ns) 0 (1) (2) (3) (4) (5) (6)
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 20 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state a. high to low propagation delay (a to b) b. low to high propagation delay (a to b) c. high to low propagation delay (b to a) d. low to high propagation delay (b to a) (1) v cc(b) = 1.2 v. (2) v cc(b) = 1.5 v. (3) v cc(b) = 1.8 v. (4) v cc(b) = 2.5 v. (5) v cc(b) = 3.3 v. (6) v cc(b) = 5.0 v. fig 13. typical propagation delay versus load capacitance; t amb = 25 ?c; v cc(a) =5v c l (pf) 35 25 530 20 10 015 001aal288 6 2 10 14 4 8 12 t phl (ns) 0 (4) (5) (6) (1) (2) (3) c l (pf) 35 25 530 20 10 015 001aal289 6 2 10 14 4 8 12 t plh (ns) 0 (4) (5) (6) (1) (2) (3) c l (pf) 35 25 530 20 10 015 001aal290 6 2 10 14 4 8 12 t phl (ns) 0 (1) (2) (3) (4) (5) (6) c l (pf) 35 25 530 20 10 015 001aal291 6 2 10 14 4 8 12 t plh (ns) 0 (1) (2) (3) (4) (5) (6)
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 21 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state 13. application information 13.1 unidirectional logic l evel-shifting application the circuit given in figure 14 is an example of the 74lvc8t245; 74lvch8t245 being used in an unidirectional l ogic level-shifting application. schematic given for one channel. fig 14. unidirectional logic level-shifting application table 15. description unidirectional logic level-shifting application name function description v cc(a) v cc1 supply voltage of system-1 (1.2 v to 5.5 v) gnd gnd device gnd a out output level depends on v cc1 voltage b in input threshold value depends on v cc2 voltage dir dir the gnd (low level) determi nes b port to a port direction v cc(b) v cc2 supply voltage of system-2 (1.2 v to 5.5 v) oe oe the gnd (low level) enables the output ports 001aak438 74lvc8t245 74lvch8t245 v cc1 system-1 system-2 v cc1 v cc2 v cc2 v cc(a) v cc(b) gnd dir bn oe an
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 22 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state 13.2 bidirectional logic l evel-shifting application figure 15 shows the 74lvc8t245; 74lvch8t245 being used in a bidirectional logic level-shifting application. ta b l e 1 6 gives a sequence that will illu strate data transmission fr om system-1 to system-2 and then from system-2 to system-1. [1] h = high voltage level; l = low voltage level; z = high-impedance off-state. 13.3 power-up considerations the device is designed such that no special power-up sequence is required other than gnd being applied first. schematic given for one channel. pull-up or pull-down only needed for 74lvc8t245. fig 15. bidirectional logic level-shifting application table 16. description bidirectional logic level-shifting application [1] state dir ctrl oe i/o-1 i/o-2 description 1 h l output input syste m-1 data to system-2 2 h h z z system-2 is getting ready to send data to system-1. i/o-1 and i/o-2 are disabled. the bus-line state depends on bus hold. 3 l h z z dir bit is set low. i/o-1 and i/o-2 still are disabled. the bus-line state depends on bus hold. 4 l l input output syste m-2 data to system-1 001aak439 pull-up/down pull-up/down 74lvc8t245 74lvch8t245 v cc1 v cc1 v cc2 v cc2 i/o-2 i/o-1 dir ctrl system-2 system-1 v cc(a) v cc(b) gnd dir b oe a oe table 17. typical total supply current (i cc(a) + i cc(b) ) v cc(a) v cc(b) unit 0 v 1.8 v 2.5 v 3.3 v 5.0 v 0 v0 < 1< 1< 1< 1 ? a 1.8 v < 1 < 2 < 2 < 2 2 ? a 2.5 v < 1 < 2 < 2 < 2 < 2 ? a 3.3 v < 1 < 2 < 2 < 2 < 2 ? a 5.0 v < 1 2 < 2 < 2 < 2 ? a
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 23 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state 14. package outline fig 16. package outline sot355-1 (tssop24) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 0.4 0.3 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot355-1 mo-153 99-12-27 03-02-19 0.25 0.5 0.2 w m b p z e 11 2 24 13 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 a max. 1.1
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 24 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state fig 17. package outline sot815-1 (dhvqfn24) references outline version european projection issue date iec jedec jeita note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. sot815-1 - - - - - - - - - 03-04-29 sot815-1 0 2.5 5 mm scale b y y 1 c c ac c b v m w m e 1 e 2 terminal 1 index area terminal 1 index area x unit a (1) max. a 1 bc e e h l e 1 ywv mm 1 0.05 0.00 0.30 0.18 0.5 4.5 e 2 1.5 0.2 2.25 1.95 d h 4.25 3.95 0.05 0.05 y 1 0.1 0.1 dimensions (mm are the original dimensions) 0.5 0.3 d (1) 5.6 5.4 e (1) 3.6 3.4 d e b a e dhvqfn24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm a a 1 c detail x e h l d h 2 23 11 14 13 12 1 24
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 25 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state 15. abbreviations 16. revision history table 18. abbreviations acronym description cdm charged device model dut device under test hbm human body model mm machine model table 19. revision history document id release date data sheet status change notice supersedes 74lvc_lvch8t245 v.3 20111212 product data sheet - 74lvc_lvch8t245 v.2 modifications: ? legal pages updated. 74lvc_lvch8t245 v.2 20110211 product data sheet - 74lvc_lvch8t245 v.1 74lvc_lvch8t245 v.1 20100111 product data sheet - -
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 26 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from competent authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74lvc_lvch8t245 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 12 december 2011 27 of 28 nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74lvc8t245; 74lvch8t245 8-bit dual supply translating transceiver; 3-state ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 12 december 2011 document identifier: 74lvc_lvch8t245 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 recommended operating conditions. . . . . . . . 5 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 5 10 dynamic characteristics . . . . . . . . . . . . . . . . . 10 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 12 typical propagation delay characteristics . . 15 13 application information. . . . . . . . . . . . . . . . . . 21 13.1 unidirectional logic level-shifting application . 21 13.2 bidirectional logic level-shifting application. . . 22 13.3 power-up considerations . . . . . . . . . . . . . . . . 22 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 26 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 26 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 17.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 18 contact information. . . . . . . . . . . . . . . . . . . . . 27 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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